Name
Title | ||
|---|---|---|
An improved test access mechanism structure and optimization technique in system-on-chip |
Abstract | ||
|---|---|---|
This paper presents a new test access mechanism (TAM) architecture and optimization method based on an improved flexible-width test bus. The method is first to set up the test time lower bound that is not depends on TAM architecture, then to construct a bus assignment that makes test time up to the lower bound. We present experimental results on our improved flexible-width test buses for four benchmark SOCs. Experiment results in a significant reduction of the test time, and is better than the proposed traditional methods in test time. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1145/1120725.1120897 | ASP-DAC |
Keywords | Field | DocType |
opc,automatic test pattern generation,dissection,lower bound,yield,system on chip | Automatic test pattern generation,Architecture,System on a chip,Upper and lower bounds,Logic testing,Computer science,Real-time computing,Electronic engineering,Embedded system | Conference |
Volume | Issue | ISSN |
2 | null | 2153-6961 |
ISBN | Citations | PageRank |
0-7803-8737-6 | 1 | 0.36 |
References | Authors | |
4 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Feng Jianhua | 1 | 1 | 1.71 |
| Jieyi Long | 2 | 129 | 8.98 |
| Xu Wenhua | 3 | 1 | 0.36 |
| Ye Hongfei | 4 | 1 | 0.36 |