Name
Abstract | ||
|---|---|---|
This paper describes how fine grain parallelism can be exploited using a behavioral synthesis tool called AccelFPGA which reads in high-level descriptions of DSP applications written in MATLAB, and automatically generates synthesizable RTL models in VHDL or Verilog. The RTL models can be synthesized using commercial logic synthesis tools and place and route tools onto FPGAs. The paper describes how powerful directives are used to provide high-level architectural tradeoffs by exploiting fine grain parallelism, pipelining, memory mapping and tiling for the DSP designer. Experimental results are reported with the AccelFPGA version 1.4 compiler on a set of 8 MATLAB benchmarks that are mapped onto the Xilinx Virtex II FPGAs. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1007/3-540-36385-8_25 | IWDC |
Keywords | Field | DocType |
matlab benchmarks,dsp designer,dsp application,exploiting fine grain parallelism,behavioral synthesis tool,fine grain parallelism,xilinx virtex ii fpgas,rtl model,commercial logic synthesis tool,high-level architectural tradeoffs,accelfpga version,place and route,logic synthesis | Logic synthesis,Computer architecture,Computer science,Parallel computing,Place and route,Field-programmable gate array,Virtex,Register-transfer level,Verilog,VHDL,Hardware description language | Conference |
Volume | ISSN | ISBN |
2571 | 0302-9743 | 3-540-00355-X |
Citations | PageRank | References |
1 | 0.35 | 3 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Prithviraj Banerjee | 1 | 2763 | 337.99 |
| Malay Haldar | 2 | 98 | 10.78 |
| Anshuman Nayak | 3 | 96 | 10.31 |
| Victor Kim | 4 | 23 | 1.45 |
| Debabrata Bagchi | 5 | 39 | 3.98 |
| Satrajit Pal | 6 | 23 | 1.45 |
| Nikhil Tripathi | 7 | 113 | 9.84 |