Name
Abstract | ||
|---|---|---|
Communication is a basic problem when using VLSI technology to implement large parallel circuits. Valuable chip area must be used to run wires connecting components on a chip and current packaging technology restricts the amount of communication that can cross chip boundaries. This paper presents a large parallel architecture for generating moves in chess and shows how it can be restructured to reduce communication and permit a straightforward VLSI implementation without any performance loss. The result is a move generator comprising 64 identical custom chips performing at a rate of 500,000 moves per second, performance that is comparable to the best existing move generator. The success of the architecture of a component module like a chess move generator depends not only on its performance but on how well it meshes with the rest of the system. We discuss the requirements of a chess move generator in the context of a chess-playing system and describe how each of these are met by our design. Details of the chip design are presented along with a description of how the move generator is built using identical chips. |
Year | DOI | Venue |
|---|---|---|
1984 | 10.1145/800015.808168 | ISCA |
Keywords | Field | DocType |
connected component,ring network,heuristic search,chip,virtual memory,np hard problems | Heuristic,Computer science,Virtual memory,Parallel computing,Real-time computing,Chip,Integrated circuit design,Packaging engineering,Series and parallel circuits,Ring network,Very-large-scale integration,Embedded system | Conference |
Volume | Issue | ISSN |
12 | 3 | 0163-5964 |
ISBN | Citations | PageRank |
0-8186-0538-3 | 4 | 4.53 |
References | Authors | |
1 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Carl Ebeling | 1 | 1405 | 185.32 |
| Andrew J. Palay | 2 | 99 | 92.63 |