Paper Info
Title
Instruction translation for an experimental S/390 processor
Abstract
The IBM™ S/390™ architecture is a complex architecture, which has grown over a long period of time. Typical implementations use microcode to cope with the more complex instructions and facilities of S/390. Current IBM S/390 processors even contain two levels of microcode.We report on an experimental S/390 processor based on a RISC processor kernel employing superscalar, out of order execution of instructions. S/390 instructions have to be translated into internal sequences of RISC instructions. Actually two closely coupled internal sequences - one for register based execution and one for storage based execution are generated. The translation is a straight-forward mapping in most cases with some flexibility for special instructions.The paper introduces the hardware mechanisms used for mapping S/390 instructions to internal sequences. The facilities, which provide a greater degree of flexibility are discussed. The interactions of the low-level mapping scheme with the microcode levels is examined. Finally we discuss our experiences with this type of implementation of a CISC architecture on a RISC processor kernel.
Year
DOI
Venue
2001
10.1145/373574.373588
SIGARCH Computer Architecture News
Keywords
Field
DocType
straight-forward mapping,cisc architecture,risc processor kernel,risc instruction,complex architecture,instruction translation,order execution,low-level mapping scheme,internal sequence,microcode level,current ibm,out of order execution
Kernel (linear algebra),Instructions per cycle,Microcode,IBM,Computer science,Computer data storage,Parallel computing,Real-time computing,Reduced instruction set computing,Complex instruction set computing,Out-of-order execution,Operating system
Journal
Volume
Issue
Citations 
29
1
2
PageRank 
References 
Authors
0.46
0
2
Name
Order
Citations
PageRank
Rolf Hilgendorf1161.78
Wolfram Sauer220.80