Name
Abstract | ||
|---|---|---|
Integrated circuits are tested thoroughly in order to meet the high demands on quality. As an additional step, outlier detection is used to detect potential unreliable chips such that quality can be improved further. However, it is often unclear to which tests outlier detection should be applied and how the parameters must be set, such that outliers are detected and yield loss remains limited. In this paper we introduce a mathematical framework, that given a set of target devices, can select tests for outlier detection and set the parameters for each outlier detection method. We provide results on real world data and analyze the resulting yield loss and missed targets. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/VTS.2013.6548885 | VTS |
Keywords | DocType | Citations |
outlier detection,potential unreliable chip,real world data,high demand,outlier detection method,additional step,resulting yield loss,mathematical framework,target device,integrated circuit | Conference | 0 |
PageRank | References | Authors |
0.34 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gerard J. M. Smit | 1 | 888 | 89.18 |
| Harm C. M. Bossers | 2 | 0 | 0.34 |
| Johann L. Hurink | 3 | 154 | 21.00 |