Name
Title | ||
|---|---|---|
GM Plan: a gate matrix layout algorithm based on artificial intelligence planning techniques |
Abstract | ||
|---|---|---|
Gate matrix layout is formulated as a planning problem where a plane (the solution steps) is generated to achieve a goal (the gate matrix layout) that consists of interacting subgoals. Each subgoal corresponds to the placement of a gate to a slot, or to the routing of a net connecting gates. The interaction among subgoals is managed with two artificial-intelligence planning techniques: hierarchical planning and metaplanning. A distance measure is defined and used to arrange the subgoals into prioritized classes in the hierarchical planning phase. Two metaplanning policies-graceful retreat and least impact-are used to decide which subgoal is to be achieved within the same priority class and how it can be achieved. In doing so, GM Plan successfully combines gate placement and net routing of the gate matrix layout into one process and has the potential to deliver better results |
Year | DOI | Venue |
|---|---|---|
1990 | 10.1109/43.57791 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | Field | DocType |
gate matrix layout algorithm,circuit layout cad,cmos integrated circuits,distance measure of connectivity,search control policy,cmos,net connecting gates,least impact,interacting subgoals,interaction among subgoals,artificial intelligence,object classification,artificial intelligence planning techniques,graceful retreat,general problem-solving heuristics,net routing,most-constraint,gate matrix layout,prioritized classes,logic arrays,distance measure,planning-based gate matrix layout,hierarchical subgoal organization,gm plan,subgoal hierarchy,search process,vlsi,problem-solving loop,priority classes,hierarchical planning,routing,domain-independent search control policies,domain-independent search control policy,artificial intelligence planning technique,search control policies,metaplanning,gate placement,subgoals interact,cmos gate matrix layout,artificial intelligence planning problem,greedy algorithms,artificial intelligent,strategic planning,circuits | Artificial intelligence planning,Matrix (mathematics),Computer science,Electronic engineering,CMOS,Greedy algorithm,Electronic circuit,Strategic planning,Very-large-scale integration | Journal |
Volume | Issue | ISSN |
9 | 8 | 0278-0070 |
Citations | PageRank | References |
16 | 1.64 | 13 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Y. H. Hu | 1 | 42 | 9.38 |
| S. -J. Chen | 2 | 16 | 1.64 |