Paper Info
Title
Iterated interpolation using a systolic array
Abstract
An implementation using systolic array logic of Aitken's method of iterated interpolation is described. The proposed design has a simple, linear topology, requires no clock, and makes only modest demands on the host computer. By overlapping the computation of successive function values, a processing element utilization of approximately 1/2 is achieved. The paper illustrates how “mathematical hardware” packages, as well as software library routines, may be part of the mathematical problem solver's tool kit in the future.
Year
DOI
Venue
1986
10.1145/6497.6500
ACM Trans. Math. Softw.
Keywords
Field
DocType
es: interpolation.. parallel computing,iterated interpolation,mathematical hardware,successive function value,mathematical problem solver,additional key words and phras,processing element utilization,systolic array,software library routine,modest demand,linear topology,host computer,proposed design,parallel computer,spanning trees,graph theory
Mathematical optimization,Computer science,Interpolation,Algorithm,Systolic array,Theoretical computer science,Host (network),Software,Linear topology,Solver,Iterated function,Computation
Journal
Volume
Issue
ISSN
12
2
0098-3500
Citations 
PageRank 
References 
11
2.13
8
Authors
1
Name
Order
Citations
PageRank
G. P. Mckeown1539.29