Name
Abstract | ||
|---|---|---|
In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port. The platform can be repeatedly reused to configure many debug structures such as assertions checkers, transaction identifiers, triggers, and event counters. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1145/1146909.1146916 | DAC |
Keywords | Field | DocType |
assertions checker,transaction identifiers,in-system functional debug,reconfigurable design-for-debug infrastructure,reconfigurable infrastructure,debug structure,event counter,jtag port,debug platform,reconfigurable fabric,design for testability,integrated circuit design,verification,performance,design,economics,system on chip | Design for testing,x86 debug register,System on a chip,Identifier,Post-silicon validation,Computer science,Integrated circuit design,Silicon debug,Debugging,Embedded system | Conference |
ISSN | ISBN | Citations |
0738-100X | 1-59593-381-6 | 160 |
PageRank | References | Authors |
10.24 | 5 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Miron Abramovici | 1 | 1441 | 117.84 |
| Paul Bradley | 2 | 217 | 12.84 |
| Kumar Dwarakanath | 3 | 160 | 10.24 |
| Peter Levin | 4 | 160 | 10.24 |
| Gerard Memmi | 5 | 160 | 10.24 |
| Dave Miller | 6 | 171 | 14.78 |