Name
Abstract | ||
|---|---|---|
Based on the observation that dynamic occurrence of zeros in the cache access stream and cache-resident memory values of ordinary programs exhibit a strong bias towards zero, this paper presents a novel CMOS five-transistor SRAM cell (5T SRAM cell) for very high density and low power cache applications. This cell retains its data with leakage current and positive feedback without refresh cycle. Novel 5T SRAM cell uses one word-line and one bit-line and extra read-line control. The new cell size is 17% smaller than a conventional six-transistor SRAM cell using same design rules with no performance degradation. Simulation and analytical results show purposed cell has correct operation during read/write and also the average dynamic energy consumption of new cell is 30% smaller than a six-transistor SRAM cell. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.4304/jcp.4.7.567-575 | JOURNAL OF COMPUTERS |
Keywords | Field | DocType |
5T SRAM cell, Read static noise margin free, Cell current, Cell leakage, Cell area, dynamic energy consumption | Cache access,Leakage (electronics),Cache,Computer science,Electronic engineering,Dynamic energy,Sram cell,Artificial intelligence,Pattern recognition,Parallel computing,High density,CMOS,Positive feedback | Journal |
Volume | Issue | ISSN |
4 | 7 | 1796-203X |
Citations | PageRank | References |
1 | 0.41 | 4 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Arash Azizi Mazreah | 1 | 12 | 2.81 |
| Mohammad Taghi Manzuri | 2 | 18 | 4.78 |
| Ali Mehrparvar | 3 | 1 | 0.75 |