Name
Abstract | ||
|---|---|---|
A “system on a chip” is described, which integrates 16 Mbits of DRAM, digital logic, SRAM, three PLLs, and a triple video digital-to-analog converter in a 0.5 micron CMOS DRAM process. Application specific integrated circuit (ASIC) techniques are employed, using multiple DRAM macros with built-in self test (BIST), full level-sensitive scan design (LSSD) logic, and externally accessible analog circuitry. Issues regarding functional debugging, DRAM macro isolation and low cost manufacturing test using only a logic tester are described |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1109/VTEST.1998.670841 | Monterey, CA |
Keywords | DocType | ISSN |
CMOS integrated circuits,VLSI,built-in self test,design for testability,mixed analogue-digital integrated circuits,production testing,0.5 micron,16 Mbit,ASIC,CMOS,DRAM macro isolation,built-in self test,design for testability,externally accessible analog circuitry,functional debugging,level-sensitive scan design logic,logic tester,low cost manufacturing test,system on a chip | Conference | 1093-0167 |
ISBN | Citations | PageRank |
0-8186-8436-4 | 0 | 0.34 |
References | Authors | |
1 | 15 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Stephen V. Kosonocky | 1 | 177 | 18.28 |
| Arthur A. Bright | 2 | 287 | 39.25 |
| Kevin W. Warren | 3 | 0 | 0.34 |
| R. A. Haring | 4 | 333 | 49.20 |
| Steve Klepner | 5 | 0 | 0.34 |
| Sameh W. Asaad | 6 | 0 | 0.34 |
| S. Basavaiah | 7 | 4 | 2.67 |
| Bob Havreluk | 8 | 0 | 0.34 |
| David Heidel | 9 | 166 | 23.01 |
| Michael Immediato | 10 | 0 | 0.34 |
| Keith A. Jenkins | 11 | 56 | 7.98 |
| Rajiv V. Joshi | 12 | 260 | 64.87 |
| Ben Parker | 13 | 0 | 0.34 |
| T. V. Rajeevakumar | 14 | 0 | 0.34 |
| Kevin G. Stawiasz | 15 | 0 | 0.34 |