Name
Title | ||
|---|---|---|
Efficient algorithm for the computation of on-chip capacitance sensitivities with respect to a large set of parameters |
Abstract | ||
|---|---|---|
Recent CAD methodologies of design-for-manufacturability (DFM) have naturally led to a significant increase in the number of process and layout parameters that have to be taken into account in design-rule checking. Methodological consistency requires that a similar number of parameters be taken into account during layout parasitic extraction. Because of the inherent variability of these parameters, the issue of efficiently extracting deterministic parasitic sensitivities with respect to such a large number of parameters must be addressed. In this paper, we tackle this very issue in the context of capacitance sensitivity extraction. In particular, we show how the adjoint sensitivity method can be efficiently integrated within a finite-difference (FD) scheme to compute the sensitivity of the capacitance with respect to a large set of BEOL parameters. If np is the number of parameters, the speedup of the adjoint method is shown to be a factor of np/2 with respect to direct FD sensitivity techniques. The proposed method has been implemented and verified on a 65 nm BEOL cross section having 10 metal layers and a total number of 59 parameters. Because of its speed, the method can be advantageously used to prune out of the CAD flow those BEOL parameters that yield a capacitance sensitivity less than a given threshold. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1145/1391469.1391699 | Anaheim, CA |
Keywords | Field | DocType |
similar number,capacitance sensitivity extraction,beol parameter,large set,total number,capacitance sensitivity,deterministic parasitic sensitivity,large number,fd sensitivity technique,on-chip capacitance sensitivity,efficient algorithm,adjoint method,adjoint sensitivity method,algorithm design and analysis,cross section,design for manufacture,cad,sparse matrices,conductors,vectors,system on a chip,design automation,monte carlo methods,design for manufacturability,design methodology,finite difference,sensitivity analysis,parasitic capacitance,process design,capacitance,design rule checking,chip,data mining,sensitivity,prototypes | Parasitic capacitance,Algorithm design,Capacitance,System on a chip,Computer science,Algorithm,Electronic engineering,Parasitic extraction,Design for manufacturability,Sparse matrix,Speedup | Conference |
ISSN | ISBN | Citations |
0738-100X | 978-1-60558-115-6 | 6 |
PageRank | References | Authors |
0.71 | 5 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tarek A. El-Moselhy | 1 | 91 | 9.34 |
| Ibrahim M. Elfadel | 2 | 153 | 40.15 |
| David Widiger | 3 | 8 | 1.45 |