Name
Abstract | ||
|---|---|---|
This paper presents an architectural simulator called VIDEOFLOW software tools for developing programmable DSP chip set for various video codec standards. This DSP chip set consists of the Image Compression Coprocessor (ICC) and Motion Estimation Coprocessor (ICC), which provide an easy solution for implementing the major digital video codec algorithms. The ICC/MEC simulation components are 100 percent bit accurate and closely approximate the timing of the actual chips. In addition, the simulation tool provides users with the ICC/MEC system simulation, debugging, and various performance monitors. This tool can also be used to define and modify the architectural specification for future product line of the ICC and MEC |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1109/ASPDAC.1995.486219 | ASP-DAC |
Keywords | DocType | ISBN |
video codec standards,architectural simulation,architectural simulator,programmable logic devices,image coding,logic cad,image compression coprocessor,circuit analysis computing,programmable dsp chip set,data compression,dsp chip set,digital signal processing chips,motion estimation,debugging,motion estimation coprocessor,simulation tool,videoflow,performance monitors,chip,image compression | Conference | 4-930813-67-0 |
Citations | PageRank | References |
0 | 0.34 | 1 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jong Tae Lee | 1 | 7 | 1.59 |
| Jaemin Kim | 2 | 0 | 0.34 |
| Jae Cheol Son | 3 | 31 | 4.07 |