Name
Abstract | ||
|---|---|---|
In this paper, negative bias temperature instability (NBTI) reliability of pFETs is analyzed under the post-fabrication SRAM self-improvement scheme that we have developed recently, where cell stability is self-improved by simply applying high stress voltage to supply voltage terminal (V-DD) of SRAM cells. It is newly found that there is no significant difference in both threshold voltage and drain current degradation by NBTI stress between fresh PFETs and PFETs after self-improvement scheme application, indicating that the self-improvement scheme has no critical reliability problem. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1587/transele.E96.C.620 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
Negative Bias Temperature Instability (NBTI), variability, SRAM, transistor, MOSFET | Self improvement,Electronic engineering,Static random-access memory,Engineering,Transistor,MOSFET,Fabrication | Journal |
Volume | Issue | ISSN |
E96C | 5 | 1745-1353 |
Citations | PageRank | References |
1 | 0.48 | 3 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nurul Ezaila Alias | 1 | 1 | 0.82 |
| Anil Kumar | 2 | 1 | 1.16 |
| Takuya Saraya | 3 | 1 | 2.17 |
| Shinji Miyano | 4 | 85 | 12.63 |
| Toshiro Hiramoto | 5 | 27 | 8.14 |