Name
Abstract | ||
|---|---|---|
Three-dimensional (3-D) IC physical design problems are usually of higher complexity, with a greatly enlarged solution space due to multiple device structure. In this paper, a new 3-D floorplanning algorithm is proposed for wirelength optimization. Our main contributions and results can be summarized as follows. First, a new hierarchical flow of 3-D floorplanning with a new inter-layer partitionin... |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/TCSI.2006.883857 | IEEE Transactions on Circuits and Systems I: Regular Papers |
Keywords | Field | DocType |
Integrated circuit interconnections,Design optimization,Very large scale integration,Power system interconnection,Simulated annealing,Engines,Large scale integration,Delay,Electronic design automation and methodology,Energy consumption | Integrated circuit layout,Simulated annealing,CAD,Computer science,Computer Aided Design,Algorithm,Electronic engineering,Physical design,Partition (number theory),Very-large-scale integration,Floorplan | Journal |
Volume | Issue | ISSN |
53 | 12 | 1549-8328 |
Citations | PageRank | References |
21 | 0.95 | 16 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhuoyuan Li | 1 | 99 | 7.08 |
| Xianlong Hong | 2 | 1307 | 132.32 |
| Qiang Zhou | 3 | 570 | 70.80 |
| Yici Cai | 4 | 1135 | 120.11 |
| Jinian Bian | 5 | 175 | 31.31 |
| Hannah H. Yang | 6 | 65 | 4.42 |
| Vijay Pitchumani | 7 | 125 | 21.38 |
| Chung-Kuan Cheng | 8 | 2314 | 285.85 |