Name
Abstract | ||
|---|---|---|
This paper presents a charge-pump based low swing interconnect receiver circuit. The interconnect circuit is single ended and supports swings of 300mV or lower. A charge pump front end at the receiver boosts the arriving signal before restoring it to the full logic level, improving the performance of the interconnect. For a 10mm long interconnect wire in a 45nm CMOS process, the proposed scheme provides 3X energy reduction at constant speed and 3.5X delay improvement at constant energy relative to prior art. We deploy the interconnect scheme as the data bus between the L1-L2 caches of a 4-core Alpha processor. Over a set of Splash benchmarks, the proposed architecture reduces total energy consumption by 70% while maintaining the same performance. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1145/2333660.2333733 | ISLPED |
Keywords | Field | DocType |
receiver circuit,constant energy,cmos process,4-core alpha processor,total energy consumption,splash benchmarks,energy reduction,proposed scheme,constant speed,proposed architecture,interconnect,front end,charge pump | Front and back ends,Interconnect bottleneck,Computer science,Voltage,Real-time computing,Electronic engineering,Logic level,Charge pump,Interconnection,Energy consumption,System bus | Conference |
Citations | PageRank | References |
0 | 0.34 | 6 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Aatmesh Shrivastava | 1 | 181 | 15.83 |
| John Lach | 2 | 1898 | 187.99 |
| Benton H. Calhoun | 3 | 1396 | 152.14 |