Name
Abstract | ||
|---|---|---|
Improving functional coverage efficiently in a verification environment based on constrained random simulation could be a difficult task, since some design states are hard to be reached by random input patterns. On the other hand, manually crafting direct test patterns may be time consuming. In this paper, a functional test pattern generation (FTPG) framework is proposed to automatically produce deterministic test patterns for complete coverage. The framework is based on the functional coverage model (covergroup) provided by SystemVerilog, and it could be easily integrated to modern digital design flow. We synthesize a practical subset of covergroup language constructs to enable FTPG by a SAT-solver. An algorithm called MRRS is proposed to minimize the potential large complexity of the synthesized circuits. Preliminary experimental results demonstrate that MRRS could facilitate FTPG to achieve 43X speed-up in average while the maximum speed-up can reach 67X. To the best of our knowledge, this is the first paper which proposes an FTPG method that utilizes covergroups. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/HLDVT.2012.6418243 | 2012 IEEE INTERNATIONAL HIGH LEVEL DESIGN VALIDATION AND TEST WORKSHOP (HLDVT) |
Keywords | Field | DocType |
formal verification,hardware description languages,computability,computational complexity | Functional verification,Computer science,Language construct,Theoretical computer science,Design flow,Formal methods,SystemVerilog,Hardware description language,Computational complexity theory,Formal verification | Conference |
ISSN | Citations | PageRank |
1552-6674 | 0 | 0.34 |
References | Authors | |
7 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| An-Che Cheng | 1 | 0 | 0.34 |
| Chia-Chih Yen | 2 | 36 | 5.65 |
| Jing-Yang Jou | 3 | 681 | 88.55 |