Name
Abstract | ||
|---|---|---|
Register allocation for instruction-level parallel processors involves problems that are not considered in register allocat,i on for scalar processors. First, when the same register is allocated to different variables, anti-dependence is gtmerated, which decreases instruction-level parallelism. Second, spill code should be inserted at a suitable position in its object, where it can be executed in parallel with other instructions. These problems do not exist for scalar processors, so existing register allocators take no account of them. This paper describes a new register allocation algorithm for solving these problems, using a graph structure that represents instructions and dependence between them. |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1145/237578.237615 | International Conference on Supercomputing 2006 |
Keywords | Field | DocType |
register allocation technique,software pipelining,register allocation | Computer architecture,List scheduling,Register allocation,Instruction scheduling,Software pipelining,Computer science,Parallel computing,Cyclic scheduling,Real-time computing | Conference |
ISBN | Citations | PageRank |
0-89791-803-7 | 2 | 0.43 |
References | Authors | |
9 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Akira Koseki | 1 | 46 | 4.73 |
| Hideaki Komatsu | 2 | 410 | 34.00 |
| Yoshiaki Fukazawa | 3 | 405 | 83.98 |