Name
Abstract | ||
|---|---|---|
In this paper the implementation of the test strategy in a so-called Very Long Instruction Word Transport Triggered Architecture (VLIW-TTA) is discussed. The complete test strategy is derived referring to the results of test synthesis, carried out in the early phase of the design. It takes the area/throughput parameters into account. The test strategy, exploiting the regularity and modularity of the VLIW-TTA structure, remains general for an arbitrary application and instantiation of the TTA processor and is based on the partial scan approach along with the functional test. The test-time analysis, in order to justify our approach and show the superiority over the classical full-scan, has been performed. The results of our strategy are shown in a few examples at the end of the paper. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1023/A:1014901829507 | Journal of Electronic Testing |
Keywords | Field | DocType |
VLIW processor test,test synthesis,Design for Testability (DfT),test-time analysis | Partial scan,Test synthesis,GSM,Very long instruction word,Computer science,Parallel computing,Transport triggered architecture,Electronic engineering,Real-time computing,Throughput,Test strategy,Modularity | Journal |
Volume | Issue | ISSN |
18 | 2 | 1530-1877 |
ISBN | Citations | PageRank |
0-7695-1016-7 | 1 | 0.36 |
References | Authors | |
7 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| V. A. Zivkovic | 1 | 1 | 0.36 |
| R. J. W. T. Tangelder | 2 | 8 | 1.64 |
| H. G. Kerkhoff | 3 | 78 | 21.89 |