Title
Modeling and Verification of Memory Architectures with AADL and REAL
Abstract
Real-Time Embedded systems must respect a wide range of non-functional properties, including safety, respect of deadlines, power or memory consumption. We note that correct hardware resource dimensioning requires taking into account the impact of the whole software, both the user code and the underlying run time environment. AADL allows one to precisely capture all of them. In this article, we evaluate the AADL modeling to define memory architectures, and then verification rules to assess that the memory is correctly dimensioned. We use the REAL domain-specific language to express memory requirements (such as layout or size) and then validate them on a case-study using the VxWorks real-time kernel.
Year
DOI
Venue
2011
10.1109/ICECCS.2011.40
ICECCS
Keywords
Field
DocType
memory architectures,correct hardware resource dimensioning,non-functional property,user code,memory consumption,underlying run time environment,vxworks real-time kernel,aadl modeling,memory requirement,memory architecture,real domain-specific language,verification,formal verification,real,embedded systems,architecture
Kernel (linear algebra),Computer science,Real-time computing,Software,Dimensioning,Memory architecture,Formal verification,Embedded system,Power consumption
Conference
Citations 
PageRank 
References 
1
0.38
3
Authors
3
Name
Order
Citations
PageRank
Stephane Rubini15712.08
Frank Singhoff29317.70
Jérôme Hugues314119.52