Paper Info
Title
An Efficient Buffer Memory System for Subarray Access
Abstract
Many current graphical display systems utilize a buffer memory system to contain a two-dimensional image array to be modified and displayed. In order to speed up the update of the buffer memory system, it is required that the buffer memory system accesses many image points within an image subarray in parallel. This paper proposes an efficient buffer memory system for a fast and high-resolution graphical display system. The memory system provides parallel accesses to $pq$ image points within a ${\rm{block(p \times q)}}$, a ${\rm{horizontal(1 \times pq)}}$, a ${\rm{vertical(pq \times 1)}}$, a forward-diagonal, or a backward-diagonal subarray in a two-dimensional image array, ${\rm{M \times N}}$, where the design parameters $p$ and $q$ are all powers of two. In the address calculation and routing circuit of the proposed buffer memory system, the address differences of the five subarrays are prearranged according to the index numbers of memory modules and stored in two Static Random Access Memories (SRAMs), so that the address differences are simply added to the base address to obtain the addresses according to the index numbers of memory modules. In addition, for the fast address calculation, one single multiplication operation in the base address calculation is replaced by a SRAM access, so that the multiplication operation can be performed during the SRAM access for the address differences for the case when N is not a power of two. The address calculation and routing circuit proposed in this paper is improved in the hardware cost, the complexity of control, and the speed over the previous circuits.
Year
DOI
Venue
2001
10.1109/71.914779
IEEE Trans. Parallel Distrib. Syst.
Keywords
Field
DocType
buffer memory system,index number,address calculation,address difference,sram access,memory module,subarray access,two-dimensional image array,base address,image point,efficient buffer memory system,base address calculation,image processing,complexity,multiplication operator,computer graphics,circuits,high resolution,static random access memory,routing,computational complexity,hardware
Interleaved memory,Semiconductor memory,Physical address,Computer science,Parallel computing,Address bus,Memory address,Memory segmentation,Computer hardware,Flat memory model,Memory buffer register,Distributed computing
Journal
Volume
Issue
ISSN
12
3
1045-9219
Citations 
PageRank 
References 
13
0.84
10
Authors
1
Name
Order
Citations
PageRank
Jong Won Park1749.56