Name
Abstract | ||
|---|---|---|
Timing errors become more and more important to dynamic performance in high-speed and high-resolution DACs. To relax the requirements on circuit design and layout complexity, two digital-delay-line (DDL) based calibration techniques for timing errors are demonstrated in this work. Matlab behavior level simulation results show that these two on-chip calibration techniques can improve the SFDR performance. The simulation results of a phase detector, the key circuit in these two calibration techniques, are given. This circuit is implemented in a CMOS 0.18mum process |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ISCAS.2006.1692532 | ISCAS |
Keywords | Field | DocType |
layout complexity,digital-to-analog converters,cmos process,cmos integrated circuits,ddl-based calibration,circuit layout,current-steering dac,timing errors,circuit complexity,delay lines,digital-delay-line,high-speed dac,high-resolution dac,0.18 micron,digital-analogue conversion,circuit design,calibration,chip,detectors,phase detector,digital delay line,phase detection,cmos technology,layout,high resolution,switches | Circuit complexity,Computer science,Circuit design,Digital delay line,Spurious-free dynamic range,CMOS,Electronic engineering,Phase detector,Detector,Calibration | Conference |
ISSN | ISBN | Citations |
0271-4302 | 0-7803-9389-9 | 4 |
PageRank | References | Authors |
0.98 | 2 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yongjian Tang | 1 | 37 | 5.04 |
| Hans Hegt | 2 | 101 | 17.59 |
| Arthur H. M. van Roermund | 3 | 379 | 67.62 |