Name
Abstract | ||
|---|---|---|
This paper presents the architecture of a fully pipelined AES encryption processor on a single chip FPGA. By using loop unrolling and inner-round and outer-round pipelining techniques, a maximum throughput of 21.54 Gbits/s is achieved. A fast and area efficient composite field implementation of the byte substitution phase is designed using an optimum number of pipeline stages for FPGA implementation. A 21.54 Gbits/s throughput is achieved using 84 Block RAMs and 5177 Slices of a VirtexII-Pro FPGA with a latency of 31 cycles and throughput per area rate of 4.2 Mbps/Slice. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/FCCM.2004.1 | FCCM |
Keywords | Field | DocType |
block rams,virtexii-pro fpga,aes encryption processor,aes processor,optimum number,byte substitution phase,area efficient composite field,maximum throughput,loop unrolling,area rate,fpga implementation,logic,chip,hardware,application specific integrated circuits,arithmetic,cryptography,field programmable gate arrays,throughput | Byte,Pipeline (computing),Advanced Encryption Standard,Computer science,Parallel computing,Field-programmable gate array,Real-time computing,Chip,Application-specific integrated circuit,Loop unrolling,Throughput | Conference |
ISBN | Citations | PageRank |
0-7695-2230-0 | 81 | 5.70 |
References | Authors | |
9 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alireza Hodjat | 1 | 329 | 22.91 |
| Ingrid Verbauwhede | 2 | 4650 | 404.57 |