Name
Abstract | ||
|---|---|---|
Advances in neuroscience have enabled researchers to develop computational models of auditory, visual and learning perceptions in the human brain. HMAX, which is a biologically inspired model of the visual cortex, has been shown to outperform standard computer vision approaches for multi-class object recognition. HMAX, while computationally demanding, can be potentially applied in various applications such as autonomous vehicle navigation, unmanned surveillance and robotics. In this paper, we present a reconfigurable hardware accelerator for the time-consuming S2 stage of the HMAX model. The accelerator leverages spatial parallelism, dedicated wide data buses with on-chip memories to provide an energy efficient solution to enable adoption into embedded systems. We present a systolic array-based architecture which includes a run-time reconfigurable convolution engine which can perform multiple variable-sized convolutions in parallel. An automation flow is described for this accelerator which can generate optimal hardware configurations for a given algorithmic specification and also perform run-time configuration and execution seamlessly. Experimental results on Virtex-6 FPGA platforms show 5X to 11X speedups and 14X to 33X higher performance-per-Watt over a CNS-based implementation on a Tesla GPU. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ASPDAC.2012.6165067 | Design Automation Conference |
Keywords | Field | DocType |
biocomputing,hearing,object recognition,CNS-based implementation,HMAX,Tesla GPU,Virtex-6 FPGA platform,algorithmic specification,auditory perception,automation flow,autonomous vehicle navigation,computational model,embedded system,human brain,learning perception,multiclass object recognition,neuromorphic object recognition,neuroscience,on-chip memories,optimal hardware configuration,reconfigurable accelerator,reconfigurable hardware accelerator,robotics,run-time configuration,run-time reconfigurable convolution engine,spatial parallelism,systolic array-based architecture,unmanned surveillance,variable-sized convolution,visual cortex,visual perception,wide data buses | Computer science,Neuromorphic engineering,Real-time computing,Automation,Electronic engineering,Artificial intelligence,Computer hardware,Robotics,Field-programmable gate array,Systolic array,Computational model,Reconfigurable computing,Cognitive neuroscience of visual object recognition | Conference |
ISSN | ISBN | Citations |
2153-6961 | 978-1-4673-0770-3 | 14 |
PageRank | References | Authors |
0.74 | 5 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jagdish Sabarad | 1 | 30 | 1.79 |
| Srinidhi Kestur | 2 | 137 | 9.47 |
| Mi Sun Park | 3 | 34 | 2.92 |
| Dharav Dantara | 4 | 29 | 1.77 |
| Narayanan Vijaykrishnan | 5 | 6955 | 524.60 |
| Yang Chen | 6 | 30 | 1.81 |
| Deepak Khosla | 7 | 42 | 5.62 |