Name
Abstract | ||
|---|---|---|
This paper develops a modular synthe- sis algorithm for timed circuits that is dramatically accelerated by partial order reduction. This algorithm synthesizes each module in a hierarchical design indi- vidually. It utilizes partial order reduction to reduce the state space explored for the other modules by con- sidering a single interleaving of concurrently enabled transitions. This approach better manages the state explosion problem resulting in a more than 2 order of magnitude reduction in synthesis time. The improved synthesis time enables the synthesis of a larger class of timed circuits than was previously possible. |
Year | Venue | Keywords |
|---|---|---|
2002 | Electr. Notes Theor. Comput. Sci. | logic synthesis,partial order reduction |
Field | DocType | Volume |
Logic synthesis,Arithmetic,Theoretical computer science,Modular design,Partial order reduction,Electronic circuit,Mathematics,Embedded system | Journal | 65 |
Issue | Citations | PageRank |
6 | 2 | 1.56 |
References | Authors | |
7 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Eric Mercer | 1 | 2 | 2.23 |
| Chris J. Myers | 2 | 607 | 75.73 |
| Tomohiro Yoneda | 3 | 353 | 41.62 |