Title
A low-power configurable neural recording system for epileptic seizure detection.
Abstract
This paper describes a low-power configurable neural recording system capable of capturing and digitizing both neural action-potential (AP) and fast-ripple (FR) signals. It demonstrates the functionality of epileptic seizure detection through FR recording. This system features a fixed-gain, variable-bandwidth (BW) front-end circuit and a sigma-delta ADC with scalable bandwidth and power consumption. The ADC employs a 2nd-order single-bit sigma-delta modulator (SDM) followed by a low-power decimation filter. Direct impulse-response implementation of a sinc(3) filter and 8-cycle data pipelining in an IIR filter are proposed for the decimation filter design to improve the power and area efficiency. In measurements, the front end exhibits 39.6-dB DC gain, 0.8 Hz to 5.2 kHz of BW, 5.86- μVrms input-referred noise, and 2.4- μW power consumption in AP mode, while showing 38.5-dB DC gain, 250 to 486 Hz of BW, 2.48- μVrms noise, and 4.5- μW power consumption in FR mode. The noise efficiency factor (NEF) is 2.93 and 7.6 for the AP and FR modes, respectively. At 77-dB dynamic range (DR), the ADC has a peak SNR and SNDR of 75.9 dB and 67 dB, respectively, while consuming 2.75-mW power in AP mode. It achieves 78-dB DR, 76.2-dB peak SNR, 73.2-dB peak SNDR, and 588- μW power consumption in FR mode. Both analog and digital power supply voltages are 2.8 V. The chip is fabricated in a standard 0.6- μm CMOS process. The die size is 11.25 mm(2).
Year
DOI
Venue
2013
10.1109/TBCAS.2012.2228857
IEEE Trans. Biomed. Circuits and Systems
Keywords
DocType
Volume
analog power supply,signal denoising,sigma-delta modulation,cmos,bioelectric potentials,medical signal detection,power consumption,neurophysiology,configurable analog-digital converter (adc),noise efficiency factor,neural action-potential signals,epilepsy,electroencephalography,deep brain stimulation (dbs),epileptic fast ripples,frequency 250 hz to 486 hz,cmos digital integrated circuits,direct impulse-response implementation,switched-capacitor circuits,2nd-order single-bit sigma-delta modulator,low-power configurable neural recording system,low-power electronics,decimation filter design,medical signal processing,fast-ripple signals,input-referred noise,neural recording interface,low-power low-noise design,sigma-delta adc,decimation filters,variable-bandwidth front-end circuit,electro encephalography,seizure,epileptic seizure detection,low-power decimation filter,gain 38.5 db,brain,power 4.5 muw,frequency 0.8 hz to 5.2 khz,size 0.6 mum,iir filter,voltage 2.8 v,sdm,digital power supply,8-cycle data pipelining,biomedical electronics,iir filters,power 2.4 muw,fr recording,pipeline processing
Journal
7
Issue
ISSN
Citations 
4
1940-9990
6
PageRank 
References 
Authors
0.50
18
4
Name
Order
Citations
PageRank
Chengliang Qian1624.90
Jess Shi260.50
Jordi Parramon3513.81
Edgar Sánchez-Sinencio469698.37