Name
Abstract | ||
|---|---|---|
With the advent of VLSI and the use of statistical simulation techniques to perform integrated circuit design, modeling of chip substrate resistance is becoming increasingly important to successful chip design. This paper will present a substrate resistance modeling technique which may be applied to the design of both FET and bipolar chips. After briefly presenting the theory behind the technique, we will describe its use in developing a substrate resistance model required for studying a disturb problem encountered with a high-speed array chip. The steps involved in building and simplifying the substrate model will be described. The effect on circuit simulations and noise sensitivity will then be shown. |
Year | DOI | Venue |
|---|---|---|
1984 | 10.1109/TCAD.1984.1270066 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
Chip Substrate Resistance Modeling,statistical simulation technique,chip substrate resistance,high-speed array chip,integrated circuit design,bipolar chip,substrate model,successful chip design,substrate resistance model,Integrated Circuit Design,circuit simulation,substrate resistance modeling technique | Journal | 3 |
Issue | ISSN | Citations |
2 | 0278-0070 | 29 |
PageRank | References | Authors |
7.52 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| T. A. Johnson | 1 | 29 | 7.52 |
| R. W. Knepper | 2 | 29 | 7.86 |
| V. Marcello | 3 | 29 | 7.52 |
| Wen Wang | 4 | 29 | 7.52 |