Name
Abstract | ||
|---|---|---|
In this paper, we propose two new N-way arbiter circuits. One circuit is based on the token-ring arbiters and another circuit is based on the mesh arbiters. The idea of the ring arbiter is to generate a lock signal by a token which is based on the non-return-to-zero signaling. It can achieve low latency and high throughput arbitration for a heavy work load environment. The idea of the mesh arbiter is to perform arbitrations between N/2 pairs at the same level and repeat them N-1 times. They can issue grant signals fairly. In this paper, we compare the performance of these N- way arbiters using 65nm process technologies qualitatively and quantitatively. We conclude that the proposed mesh arbiters are suitable when the number of inputs is 5 or less. We also conclude that we must select the appropriate arbiters considering tradeoff between latency, throughput, area, and energy when the number of inputs is larger than 5. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ICCD.2009.5413164 | Lake Tahoe, CA |
Keywords | Field | DocType |
low latency,heavy work load environment,high throughput arbitration,appropriate arbiter,n-1 time,token-ring arbiter,n-way ring,proposed mesh arbiter,ring arbiter,mesh arbiter,new n-way arbiter circuit,square arbiter,logic gates,topology,layout,throughput,high throughput,non return to zero | Arbiter,Logic gate,Lock (computer science),Computer science,Latency (engineering),Parallel computing,Computer network,Real-time computing,Latency (engineering),Throughput,Electronic circuit,Security token | Conference |
ISSN | ISBN | Citations |
1063-6404 E-ISBN : 978-1-4244-5028-2 | 978-1-4244-5028-2 | 1 |
PageRank | References | Authors |
0.38 | 4 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Masashi Imai | 1 | 47 | 6.24 |
| Tomohiro Yoneda | 2 | 353 | 41.62 |
| Takashi Nanya | 3 | 200 | 35.46 |