Paper Info
Title
Design of Low Power Two-phase CMOS Buffer for Large capacitive loading Applications.
Abstract
In this paper, a low power two-phase CMOS buffer with short-circuit power elimination and charge reuse for non-speed-critical large capacitive loading applications is proposed. The short-circuit power eliminating circuit is designed to remove the short-circuit current at the buffer's output, which accounts for the largest portion of the short-circuit power dissipation of the CMOS buffer. The charge reuse circuit is used to reduce the output dynamic power dissipation of the two-phase buffer. Moreover, the overall power dissipation of the proposed buffer is further decreased by optimizing the number of tapered stages and the values of tapered factors in the tapered chains of the short-circuit power eliminating circuit. In order to validate the efficiency of the proposed design, theoretical analysis and simulations with various capacitive loads are conducted using TSMC 0.18-mu m 1P6M and UMC advanced 90-nm 1P9M CMOS technologies. The results show that the power dissipation of the proposed two-phase CMOS buffer is 8.6% lower than that of the conventional two-phase CMOS tapered buffer. The power-delay product of the proposed buffer is 2.7% smaller than that of the conventional tapered buffer.
Year
DOI
Venue
2013
10.1142/S0218126612500922
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS
Keywords
Field
DocType
Power dissipation,two-phase,CMOS buffer,short-circuit power,dynamic power,charge reuse
Reuse,Dissipation,Computer science,Capacitive sensing,Electronic engineering,CMOS,Dynamic power dissipation,Dynamic demand,Electrical engineering
Journal
Volume
Issue
ISSN
22
2
0218-1266
Citations 
PageRank 
References 
0
0.34
10
Authors
2
Name
Order
Citations
PageRank
Hung-Yi Lin1398.74
Yen-tai Lai210018.18