Name
Abstract | ||
|---|---|---|
This paper describes an experience in applying formal techniques to the verification of the IP cores composing a DSP. We discuss the application methods and highlight the complementary aspect with traditional simulation. The paper concludes with comments on the results and a discussion on further improvements of the methods elaborated in this experience. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/HLDVT.2002.1224440 | HLDVT |
Keywords | Field | DocType |
dsp ip core,traditional simulation,application method,ip core,model checking,formal technique,complementary aspect,formal verification | Formal equivalence checking,Functional verification,Model checking,Intelligent verification,Computer science,Runtime verification,Theoretical computer science,Verification,High-level verification,Formal verification | Conference |
ISBN | Citations | PageRank |
0-7803-7655-2 | 0 | 0.34 |
References | Authors | |
0 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| H. -N. Nguyen | 1 | 1 | 1.44 |
| P. Koumou | 2 | 0 | 0.34 |
| Candaele, B. | 3 | 5 | 1.21 |
| M. Sarlotte | 4 | 3 | 1.16 |
| C. Antoine | 5 | 0 | 0.34 |
| Emeriau, S. | 6 | 2 | 1.06 |