Abstract | ||
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We design, implement and evaluate a power-efficient and traffic-aware transcoding system on multicore servers that appropriately adjusts the processor operating level. The system is capable of configuring the number of active cores and core frequency “on-the-fly” according to the varying traffic rate. Results on an AMD machine show that our system saves 51.0% power consumption compared to a native system without power-saving schemes. It also outperforms three other power-aware systems, CG (clock gating), C-DVFS (chip-wide DVFS) and Hybrid (chip-wide DVFS + power-gating), by 19.5%, 10.5% and 5.5% reduction of power consumption, respectively. |
Year | DOI | Venue |
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2010 | 10.1145/1872007.1872044 | ANCS |
Keywords | Field | DocType |
optimisation,power optimization,chip-wide dvfs,power aware computing,power consumption,core frequency,amd machine,multicore architecture,amd machine show,power-aware system,native system,multiprocessing systems,clock gating,multimedia transcoding,media streaming,active core,transcoding,multicore server,processor operating level,traffic aware transcoding system,traffic-aware transcoding system,mathematical model,servers,chip,multicore processing,power efficiency | Clock gating,Transcoding,Power optimization,Computer science,Server,Real-time computing,Power demand,Multicore architecture,Multi-core processor,Power consumption,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-4503-0379-8 | 2 | 0.39 |
References | Authors | |
3 | 3 |
Name | Order | Citations | PageRank |
---|---|---|---|
Jilong Kuang | 1 | 38 | 17.00 |
Danhua Guo | 2 | 101 | 6.66 |
Laxmi N. Bhuyan | 3 | 2393 | 248.44 |