Name
Abstract | ||
|---|---|---|
Digital-pin methods are cost-effective for total jitter (TJ) tests, because no additional hardware or instrumentation is required. Furthermore they can coexist with functional test. An SoC tester implements the per-pin timing jitter scope method and the PDF blind separator method, which accurately estimates both RJ & DJ, to guarantee the BER performance of a TX PHY under test. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ATS.2008.38 | ATS '08 Proceedings of the 2008 17th Asian Test Symposium |
Keywords | Field | DocType |
per-pin timing jitter scope,total jitter measurement,tx phy,ber performance,additional hardware,pdf blind separator method,soc tester,total jitter,digital-pin method,testing hsio integrated socs,functional test,cost effectiveness,system on chip,bit error rate,histograms,gaussian distribution,ber,system on a chip,testing,jitter | Histogram,System on a chip,Computer science,Production testing,Real-time computing,Electronic engineering,Jitter,Bit error rate,Embedded system,Instrumentation | Conference |
ISSN | ISBN | Citations |
1081-7735 | 978-0-7695-3396-4 | 1 |
PageRank | References | Authors |
0.38 | 2 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Takahiro J. Yamaguchi | 1 | 176 | 35.24 |
| Masahiro Ishida | 2 | 105 | 22.58 |