Name
Abstract | ||
|---|---|---|
We present an all-digital monitor structure to measure the Write Margin (WM) with dynamic Word-Line (WL) pulse for standard CMOS 6T SRAM. Ring oscillator and frequency divider based structures are used to generate wide range WL pulses (150ps ~ 32ns) with resolution of 50ps. The bit-line voltage is then successively stepped down for dynamic Write Margin characterization under given word-line pulse width. An improved Skitter based structure is employed to measure the WL pulse width with resolution of 10 ~ 20ps. Implementation of a 256Kb test chip in UMC 55nm Standard Performance (SP) CMOS technology is described. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/APCCAS.2012.6418985 | APCCAS |
Keywords | Field | DocType |
cmos 6t sram,dynamic write margin characterization,sram chips,frequency divider based structure,all-digital monitor structure,size 55 nm,ring oscillator,dynamic word-line pulse write margin monitor,umc standard performance cmos technology,frequency dividers,skitter based structure,memory size 6 tbyte,write margin measurement,memory size 256 kbyte,oscillators,cmos memory circuits | Ring oscillator,Frequency divider,Computer science,Voltage,Pulse-width modulation,Static random-access memory,Electronic engineering,CMOS,Pulse (signal processing),Chip | Conference |
ISBN | Citations | PageRank |
978-1-4577-1728-4 | 1 | 0.37 |
References | Authors | |
3 | 11 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shao-Cheng Wang | 1 | 43 | 5.63 |
| Geng-Cing Lin | 2 | 9 | 2.54 |
| Yi-Wei Lin | 3 | 12 | 3.66 |
| Ming-Chien Tsai | 4 | 87 | 7.34 |
| Yi-Wei Chiu | 5 | 26 | 3.00 |
| Shyh-Jye Jou | 6 | 420 | 275.67 |
| Ching-Te Chuang | 7 | 465 | 76.52 |
| Nan-Chun Lien | 8 | 13 | 4.18 |
| Wei-Chiang Shih | 9 | 39 | 4.41 |
| Kuen-Di Lee | 10 | 48 | 6.10 |
| Jyun-Kai Chu | 11 | 2 | 0.74 |