Name
Abstract | ||
|---|---|---|
The problems of placement and routing are without doubt the most time-consuming part of the process of automatically synthesizing and configuring circuits for field-programmable gate arrays (FPGAs). FPGAs offer the ability to quickly reconfigure circuits to support rapid prototyping, emulation, or configurable computing, but the time to perform placement and routing, which can take many hours, has... |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/43.856973 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
Routing,Field programmable gate arrays,Convergence,Delay,Switches,Costs,Circuit synthesis,Prototypes,Emulation,Concurrent computing | Journal | 19 |
Issue | ISSN | Citations |
8 | 0278-0070 | 10 |
PageRank | References | Authors |
0.74 | 7 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pak K. Chan | 1 | 357 | 58.09 |
| Martine D. F. Schlag | 2 | 303 | 47.90 |
| Carl Ebeling | 3 | 1405 | 185.32 |
| Larry McMurchie | 4 | 481 | 40.41 |