Paper Info
Title
SS-KTC: A High-Testability Low-Overhead Scan Architecture with Multi-level Security Integration
Abstract
Scan testing has been proven to leak secret information through side-channel attacks. To ensure high security when testing crypto chips without compromising testability, a new secure scan architecture with key authorized test controlling is proposed. In this method, multiple test keys are uniquely integrated into the test vectors by employing a special key fill technique without increasing the test overhead in terms of test time and test data volume. The scan test process is properly initiated and operated relying on multiple levels of security authorization. With the key authorized test controlling scheme, the scan chains may be blocked against shifting out secure information to unauthorized users. The experimental results demonstrate the robustness of the proposed secure scan architecture while achieving the lowest test and hardware overhead compared to the existing approaches.
Year
DOI
Venue
2009
10.1109/VTS.2009.20
VTS
Keywords
Field
DocType
test vector,test time,multiple test key,test process,lowest test,test data volume,high-testability low-overhead scan architecture,test overhead,secure information,key authorized test controlling,key authorized test,multi-level security integration,cryptography,authorisation,security testing,registers,controllability,side channel attacks,chip,information security,computer architecture,data security,hardware,multiple testing,security authorization,observability,security,testing,side channel attack,authorization
Testability,Data security,Observability,Computer science,Cryptography,Information security,Robustness (computer science),Test data,Side channel attack,Embedded system
Conference
ISSN
Citations 
PageRank 
1093-0167
16
0.89
References 
Authors
16
2
Name
Order
Citations
PageRank
Unni Chandran1221.79
Dan Zhao2383.54