Title
Using unified power format standard concepts for power-aware design and verification of systems-onchip at transaction level.
Abstract
Building efficient and correct system power-management strategies relies on efficient power architecture decision making as well as respecting structural dependencies induced by such architecture. Transaction level modelling allows a rapid exploration, verification and evaluation of alternative power-management architectures and strategies. This study introduces an efficient methodology for making...
Year
DOI
Venue
2012
10.1049/iet-cds.2011.0352
IET Circuits, Devices & Systems
Keywords
Field
DocType
decision making,IEEE standards,power aware computing,system-on-chip
Unified Power Format,Architecture,Power optimization,Software engineering,Computer science,Assertion,Electronic engineering,Database transaction,Power Architecture,Common Power Format,Embedded system
Journal
Volume
Issue
ISSN
6
5
1751-858X
Citations 
PageRank 
References 
13
1.21
5
Authors
3
Name
Order
Citations
PageRank
Ons Mbarek1222.72
Alain Pegatoquet213519.71
Michel Auguin323835.10