Name
Abstract | ||
|---|---|---|
The sequential minimal optimization (SMO) algorithm has been widely used for training the support vector machine (SVM). In this paper, we present the first chip design for sequential minimal optimization. This chip is implemented as an intellectual property (IF) core, suitable to be utilized in an SVM-based recognition system on a chip. The proposed SMO chip has been tested to be fully functional, using a prototype system based on the Altera DE2 board with Cyclone II 2C70 FPGA (field-programmable gate array). |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ISCAS.2009.5118311 | ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5 |
Keywords | Field | DocType |
computer architecture,prototypes,intellectual property,sequential minimal optimization,integrated circuit design,vlsi design,support vector machine,chip scale packaging,field programmable gate array,algorithm design and analysis,cyclones,vlsi,support vector machines,chip,learning artificial intelligence,design optimization,field programmable gate arrays,system on a chip,optimization,very large scale integration,kernel,prediction algorithms,system testing | Algorithm design,Computer science,Support vector machine,Field-programmable gate array,Algorithm,Electronic engineering,Chip,Gate array,Integrated circuit design,Sequential minimal optimization,Very-large-scale integration | Conference |
Citations | PageRank | References |
2 | 0.52 | 3 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ta-Wen Kuan | 1 | 37 | 6.59 |
| Jhing-fa Wang | 2 | 982 | 114.31 |
| Jia-Ching Wang | 3 | 515 | 58.13 |
| Gaung-Hui Gu | 4 | 22 | 1.85 |