Name
Title | ||
|---|---|---|
An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts |
Abstract | ||
|---|---|---|
With technology scaling, the trend for high performance integrated circuits is towards ever higher operating frequency, lower power supply voltages and higher power dissipation. This causes a dramatic increase in the currents being delivered through the on-chip power grid and is recognized in the International Technology Roadmap for Semiconductors as one of the difficult challenges. The addition of decoupling capacitances (decaps) is arguably the most powerful degree of freedom that a designer has for power-grid noise abatement and is becoming more important as technology scales. In this paper, we propose and demonstrate an algorithm for the automated placement and sizing of decaps in ASIC-like circuits. The adjoint sensitivity method is applied to calculate the first-order sensitivity of the power grid noise with respect to every decap. We propose a fast convolution technique based on piecewise linear (PWL) compressions of the original and adjoint waveforms. Experimental results show that power grid noise can be significantly reduced after a judicious optimization of decap placement, with little change of the total chip area. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1145/505388.505405 | ISPD |
Keywords | Field | DocType |
placement,power-grid noise abatement,automated placement,first-order sensitivity,optimization,lower power supply voltage,adjoint sensitivity,higher power dissipation,asics,adjoint waveform,decap placement,standard cell layout,power grid noise,optimal decoupling capacitor sizing,on-chip power grid,adjoint sensitivity method,decoupling capacitor,integrated circuit,piecewise linear,power dissipation,degree of freedom,first order,chip | Mathematical optimization,Computer science,Control theory,Decoupling (cosmology),Noise control,Algorithm,Chip,International Technology Roadmap for Semiconductors,Decoupling capacitor,Sizing,Standard cell,Integrated circuit | Conference |
ISBN | Citations | PageRank |
1-58113-460-6 | 47 | 2.84 |
References | Authors | |
13 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Haihua Su | 1 | 405 | 27.32 |
| Sachin Sapatnekar | 2 | 4074 | 361.60 |
| Sani R. Nassif | 3 | 2268 | 247.45 |