Name
Abstract | ||
|---|---|---|
Editor's note: This article uses simulation to bridge the gap between specification and formal verification of high-level models and simulation of RTL models. The authors apply their practical, two-phase procedure for defining the refinement map to the Alpha 21364 multiprocessing hardware. The methodology and tools they present can improve simulation coverage. 驴Carl Pixley, Synopsys |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/MDT.2004.94 | IEEE Design & Test of Computers |
Keywords | Field | DocType |
two-phase procedure,refinement map,high-level model,linking simulation,higher level,multiprocessing hardware,rtl model,simulation coverage,carl pixley,formal verification,logic simulation,modeling and simulation,automatic test pattern generation,formal specification | Formal equivalence checking,Programming language,Computer science,Intelligent verification,Correctness,Formal specification,Logic simulation,Refinement,Formal methods,Formal verification | Journal |
Volume | Issue | Citations |
21 | 6 | 9 |
PageRank | References | Authors |
0.63 | 9 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Serdar Tasiran | 1 | 1030 | 79.90 |
| Yuan Yu | 2 | 2955 | 149.84 |
| Brannon Batson | 3 | 270 | 21.72 |