Paper Info
Title
A CMOS Image Sensor With On-Chip Image Compression Based on Predictive Boundary Adaptation and Memoryless QTD Algorithm
Abstract
This paper presents the architecture, algorithm, and VLSI hardware of image acquisition, storage, and compression on a single-chip CMOS image sensor. The image array is based on time domain digital pixel sensor technology equipped with nondestructive storage capability using 8-bit Static-RAM device embedded at the pixel level. The pixel-level memory is used to store the uncompressed illumination data during the integration mode as well as the compressed illumination data obtained after the compression stage. An adaptive quantization scheme based on fast boundary adaptation rule (FBAR) and differential pulse code modulation (DPCM) procedure followed by an online, least storage quadrant tree decomposition (QTD) processing is proposed enabling a robust and compact image compression processor. A prototype chip including 64×64 pixels, read-out and control circuitry as well as an on-chip compression processor was implemented in 0.35 μm CMOS technology with a silicon area of 3.2×3.0 mm2 and an overall power of 17 mW. Simulation and measurements results show compression figures corresponding to 0.6-1 bit-per-pixel (BPP), while maintaining reasonable peak signal-to-noise ratio levels.
Year
DOI
Venue
2011
10.1109/TVLSI.2009.2038388
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Keywords
Field
DocType
fast boundary adaptation rule,dpcm procedure,power 17 mw,image coding,word length 8 bit,quadrant tree decomposition (qtd),random-access storage,cmos image sensors,peak signal-to-noise ratio levels,uncompressed illumination data,on-chip compression processor,static-ram device,pixel-level memory,quantisation (signal),data compression,fbar procedure,time domain digital pixel sensor technology,image compression processor,single-chip cmos image sensor,size 0.35 mum,least storage quadrant tree decomposition processing,illumination data,image array,differential pulse code modulation,time-domain analysis,image acquisition,vlsi,on-chip image compression,vlsi hardware,adaptive quantization scheme,memoryless qtd algorithm,nondestructive storage capability,cmos image sensor,compression stage,storage quadrant tree decomposition,compact image compression processor,image storage,hilbert scan,compression figure,predictive boundary adaptation,cmos technology,sensor array,peak signal to noise ratio,very large scale integration,tree decomposition,bits per pixel,image compression,pixel,time domain,hardware,lighting,pulse modulation,chip
Pulse-code modulation,Image sensor,Computer science,Algorithm,Electronic engineering,Chip,CMOS,Pixel,Data compression,Computer hardware,Image compression,Uncompressed video
Journal
Volume
Issue
ISSN
19
4
1063-8210
Citations 
PageRank 
References 
18
1.11
11
Authors
3
Name
Order
Citations
PageRank
Shoushun Chen117726.85
Amine Bermak249390.25
Yan Wang3181.45