Title
Mapping to reduce contention in multiprocessor architectures
Abstract
Reducing communication overhead has been widely recognized as a requirement for achieving efficient mappings which substantially reduce the execution time of parallel algorithms. This paper presents an iterative heuristic for static mapping of parallel algorithms to architectures. Special attention is given to measuring and reducing channel contention. Experimental results are used to show the effects of channel contention for packet-switched networks and the improvement realized by the authors' heuristic. They also present preliminary results for wormhole-routed networks.
Year
DOI
Venue
1993
10.1109/IPPS.1993.262889
Newport, CA
Keywords
Field
DocType
parallel algorithm,resource allocation,network topology,computational modeling,concurrent computing,parallel algorithms,computer architecture,information science
Static mapping,Heuristic,Parallel algorithm,Computer science,Parallel computing,Multiprocessing,Network topology,Resource allocation,Execution time,Concurrent computing,Distributed computing
Conference
ISBN
Citations 
PageRank 
0-8186-3442-1
3
0.58
References 
Authors
7
2
Name
Order
Citations
PageRank
Loren Schwiebert187190.17
D. N. Jayasimha215816.02