Name
Abstract | ||
|---|---|---|
This brief presents an in-place computing design for the deblocking filter used in H.264/AVC video coding standard. The proposed in-placed computing flow reuses intermediate data as soon as data is available. Thus, the intermediate data storage is reduced to only the four 4 × 4 blocks instead of whole 16 × 16 macroblock. The resulting design can achieve 100 MHz with only 13.41K gate count and support real-time deblocking operation of 2K × 1K@30 Hz video application when clocked at 73.73 MHz by using 0.25-μm CMOS technology. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/TCSII.2006.875323 | IEEE Trans. on Circuits and Systems |
Keywords | Field | DocType |
h.264/avc,0.25 micron,deblocking filter,73.73 mhz,real-time deblocking,video coding standard,cmos technology,digital filters,logic design,video coding,cmos digital integrated circuits,intermediate data storage,vlsi architecture design,100 mhz,30 hz,bandwidth,memory,real time,transform coding,computer architecture,data storage,very large scale integration | Macroblock,Gate count,Digital filter,Computer data storage,Computer science,Transform coding,Electronic engineering,CMOS,Bandwidth (signal processing),Deblocking filter,Embedded system | Journal |
Volume | Issue | ISSN |
53 | 7 | 1549-7747 |
Citations | PageRank | References |
25 | 1.59 | 6 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chao-Chung Cheng | 1 | 280 | 22.04 |
| Tian-Sheuan Chang | 2 | 712 | 69.10 |
| Kun-bin Lee | 3 | 126 | 10.54 |