Name
Title | ||
|---|---|---|
Allowing cycle-stealing direct memory access I/O concurrent with hard-real-time programs |
Abstract | ||
|---|---|---|
Hard-real-time schedulability analysis is carried out based on the assumption that the worst-case execution time (WCET) of each task is known. Cycle-stealing Direct Memory Access (DMA) I/O steals bus cycles from an executing program and prolongs the execution time of the program. Because of the difficulty in bounding the interference on the executing program, cycle-stealing DMA I/O is often disabled in hard-real-time systems. This paper presents an analytical method for bounding the WCET of a program executing concurrently with cycle-stealing DMA I/O. This is an extension of our previous work which bounded the WCET of a straight-line sequence of instructions when cycle-stealing operations are allowed. We demonstrate the effectiveness of our method with experiments on several programs. |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/ICPADS.1996.517590 | ICPADS |
Keywords | Field | DocType |
hard-real-time system,execution time,hard-real-time program,cycle-stealing dma,bus cycle,cycle-stealing operation,worst-case execution time,cycle-stealing direct memory access,hard-real-time schedulability analysis,direct memory access,previous work,analytical method,computer science,worst case execution time,pipelines,reduced instruction set computing,assembly,frequency,real time systems | Cycle stealing,Computer science,Input/output,Real-time computing,Direct memory access,Distributed computing,Worst-case execution time,Parallel computing,Reduced instruction set computing,Execution time,Embedded system,Bounded function,Bounding overwatch | Conference |
ISBN | Citations | PageRank |
0-8186-7267-6 | 7 | 0.72 |
References | Authors | |
7 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Taiyi Huang | 1 | 256 | 33.43 |
| J. W.-S. Liu | 2 | 451 | 34.30 |
| Jen-Yao Chung | 3 | 1489 | 243.42 |