Title
A Novel Double-Data-Rate AES Architecture Resistant against Fault Injection
Abstract
Several techniques have been proposed for encryption blocks in order to provide protection against faults. These techniques usually exploit some form of redundancy, e.g. by means of error detection codes. However, protection schemes that offer an acceptable error detection rate are in general expensive, while temporal redundancy heavily affects the throughput. In this paper, we propose a new design solution that exploits temporal redundancy by DDR techniques without affecting adversely the throughput at lower clock frequencies. We will also show that the overall costs can be comparable to other solutions recently proposed.
Year
DOI
Venue
2007
10.1109/FDTC.2007.1
FDTC
Keywords
Field
DocType
advanced encryption standard,error detection,double data rate,redundancy,cryptography
Computer science,Triple modular redundancy,Real-time computing,Encryption,Error detection and correction,Redundancy (engineering),Redundancy (information theory),Throughput,Fault injection,Double data rate,Embedded system
Conference
ISBN
Citations 
PageRank 
0-7695-2982-8
10
0.75
References 
Authors
9
3
Name
Order
Citations
PageRank
Paolo Maistri124520.35
Pierre Vanhauwaert21178.40
Régis Leveugle335444.83