Name
Abstract | ||
|---|---|---|
The steep sub-threshold characteristics of inter-band tunneling FETs (TFETs) make an attractive choice for low voltage operations. In this work, we propose a hybrid TFET-CMOS chip multiprocessor (CMP) that uses CMOS cores for higher voltages and TFETs for lower voltages by exploiting differences in application characteristics. Building from the device characterization to design and simulation of TFET based circuits, our work culminates with a workload evaluation of various single/multi-threaded applications. Our evaluation shows the promise of a new dimension to heterogeneous CMPs to achieve significant energy efficiencies (upto 50% energy benefit and 25% ED benefit with single-threaded applications, and 55% ED benefit with multi-threaded applications). |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1145/2024724.2024889 | Design Automation Conference |
Keywords | Field | DocType |
attractive choice,hybrid tfet-cmos core,application characteristic,ed benefit,significant energy efficiency,workload evaluation,heterogeneous cmps,multi-threaded application,energy-efficient heterogeneous cmp,cmos core,device characterization,energy benefit,cmos integrated circuits,energy efficient,tunneling,integrated circuit,field effect transistors,logic gate,low voltage,logic gates | Logic gate,Efficient energy use,Field-effect transistor,Computer science,Voltage,Electronic engineering,CMOS,Chip,Low voltage,Electronic circuit,Electrical engineering | Conference |
ISSN | ISBN | Citations |
0738-100x | 978-1-4503-0636-2 | 29 |
PageRank | References | Authors |
2.04 | 10 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vinay Saripalli | 1 | 145 | 13.54 |
| Asit K. Mishra | 2 | 1216 | 46.21 |
| Suman Datta | 3 | 415 | 51.93 |
| Narayanan Vijaykrishnan | 4 | 6955 | 524.60 |