Name
Abstract | ||
|---|---|---|
The primary intent of this paper is to present an innovative verification and validation paradigm for both software and systems engineering design models. We consider here two mainstream languages that are UML and SysML. The proposed paradigm relies mainly on formal methods providing a better assessment when used as complementary to ubiquitous techniques such as simulation. Moreover, we advocate the use of software engineering and program analysis techniques in order to augment the results of the aforementioned formal methods. To validate the proposed approach, we designed and implemented an integrated and automated environment capable of assessing software and systems engineering design models. We illustrate our methodology when applied to the assessment of class and package diagrams and the verication of work ow systems modeled using activity diagrams. |
Year | Venue | Keywords |
|---|---|---|
2006 | ACST | model checking,software engineering,uml,sysml,verification and validation |
Field | DocType | ISBN |
Verification and validation of computer simulation models,UML tool,Software engineering,Computer science,Applications of UML,Formal methods,Software verification and validation,Systems Modeling Language,Metamodeling,Software verification | Conference | 0-88986-545-0 |
Citations | PageRank | References |
0 | 0.34 | 4 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Luay Alawneh | 1 | 70 | 9.18 |
| Mourad Debbabi | 2 | 1467 | 144.47 |
| Fawzi Hassaïne | 3 | 16 | 2.14 |
| Andrei Soeanu | 4 | 43 | 7.49 |