Paper Info
Title
Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs
Abstract
Under the current process and layer bonding technology for the TSV (through-silicon-via) based 3D ICs, it is known that the TSV resource is one of the major sources of the function failure of the chip. Furthermore, TSV takes much larger size and pitch than the normal logic components. For this reason, a careful allocation of the TSV resource has been required in 3D IC designs, and several works have been proposed to allocate minimal TSVs. This work also addresses the problem of TSV allocation and optimization, but overcomes one of the critical limitations of the previous works, which is the unawareness or no exploitation of the possibility of TSV resource sharing, previously merely resorting to a simple binding of the data transfers to TSVs. This is because the previous 3D layer partitioners have performed TSV allocation and minimization without any link to the data transfer information accessible from the high-level synthesis flow. This work proposes a set of TSV resource sharing and optimization algorithms (as a post-processing of 3D layer partitioning) by utilizing the life time information of the data transfers taken from the high-level synthesis. Specifically, we propose three algorithms for TSV resource sharing and optimization, which can be selectively applied depending on the sharing granularity and design complexity: (1) word-level TSV sharing, (2) bit-level TSV sharing, and (3) TSV refinement combined with register replication. Through experiments with benchmark designs, it is confirmed that our proposed algorithms are able to reduce the number of TSVs by 41.1% on average in word-level TSV sharing and 26.0% in bit-level TSV sharing compared with the results produced by the conventional layer partitioning with no TSV sharing while still meeting the timing constraint of designs.
Year
DOI
Venue
2014
10.1016/j.vlsi.2013.11.001
Integration
Keywords
Field
DocType
tsv resource sharing,tsv refinement,word-level tsv sharing,bit-level tsv,tsv resource,sharing granularity,bit-level tsv sharing,tsv sharing,conventional layer,tsv allocation,high level synthesis,resource sharing
Data transmission,Computer science,High-level synthesis,Algorithm,Real-time computing,Electronic engineering,Chip,Minification,Three-dimensional integrated circuit,Granularity,Shared resource,Life time
Journal
Volume
Issue
ISSN
47
2
0167-9260
Citations 
PageRank 
References 
4
0.43
21
Authors
2
Name
Order
Citations
PageRank
Byunghyun Lee1293.46
Taewhan Kim21087113.31