Name
Abstract | ||
|---|---|---|
This paper presents the implementation of a coarse-grained Magnetic RAM based Reconfigurable Array. The Reconfigurable Array architecture is organized as a one-dimensional array of programmable ALU, with the configuration bits stored in magnetic random-access memories. The use of MRAM technology to implement run-time reconfigurable hardware devices is a very promising technological solution because MRAM can provide non-volatility with cell areas and access speeds comparable to those of SRAM, and with lower process complexity than flash memory. This type of coarse-grained array, where each reconfigurable element computes on 4-bit or larger input words, is more suitable to execute data-oriented algorithms and is more able to exploit larger amounts of operation-level parallelism than common fine-grained architectures. By substantially reducing the overhead for configurability, this coarse-grain architecture is also more apt to efficiently exploit run-time reconfiguration and therefore to take advantage of multi-context MRAM-based configuration memories. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/DSD.2009.198 | DSD |
Keywords | Field | DocType |
run-time reconfigurable array,magnetic ram,transistors,sram,generators,mram | Reconfigurable array,Flash memory,Computer science,Parallel computing,Static random-access memory,Magnetoresistive random-access memory,Exploit,Transistor,Computer hardware,Control reconfiguration,Reconfigurable computing | Conference |
Citations | PageRank | References |
3 | 0.47 | 7 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Victor Silva | 1 | 5 | 2.24 |
| Luis B. Oliveira | 2 | 13 | 2.02 |
| Jorge R. Fernandes | 3 | 154 | 34.16 |
| Mario P. Vestias | 4 | 6 | 1.63 |
| Horácio C. Neto | 5 | 172 | 24.25 |