Name
Abstract | ||
|---|---|---|
Binary block codes are constructed that are capable of correcting successive timing errors such as the deletion or insertion of bits within a single additive burst of errors of length or less , where and are the design parameters that specify the length of correctable successive timing errors and is the length of the correctable additive burst. A decoding algorithm is given and the efficiency of these codes is discussed. |
Year | DOI | Venue |
|---|---|---|
1980 | 10.1109/TIT.1980.1056219 | IEEE Transactions on Information Theory |
Keywords | Field | DocType |
successive timing error,correctable successive timing error,block codes,correctable additive burst,design parameter,single additive burst,sleq d,decoding algorithm,synchronization,binary block code,insertion ofsbits,atomic clocks,reliability engineering,error correction,additives,decoding | Hamming code,Synchronization,Error floor,Computer science,Block code,Binary block codes,Burst error-correcting code,Algorithm,Arithmetic,Decoding methods | Journal |
Volume | Issue | ISSN |
26 | 4 | 0018-9448 |
Citations | PageRank | References |
1 | 0.36 | 3 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| I. Iizuka | 1 | 1 | 0.36 |
| M. Kasahara | 2 | 19 | 7.52 |
| Toshihiko Namekawa | 3 | 90 | 107.56 |