Name
Abstract | ||
|---|---|---|
An effective layout design method for VLSI processors, called the `macrocell approach' is presented. The approach bridges the gap between full manual layout and polycell/standard cell layout with respect to the design productivity and the performance. After precise floorplanning, functional blocks are designed into macrocells using a flexible symbolic layout method, and a VLSI chip is laid out by an automatic layout program. A 16-bit digital signal processor (DSP) was designed using 2-μm CMOS technology. Both high packing density of 1150 transistors/mm2 and high productivity of 6.5 transistors/day for symbolic layout were attained in the design. After fabrication, the chip operated with the first silicon, realizing high-speed operation in an application program for a 32-kb/s ADPCM CODEC (adaptive differential pulse-code modulated coder-decoder) |
Year | DOI | Venue |
|---|---|---|
1988 | 10.1109/43.16805 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
full manual layout,CMOS integrated circuits,vlsi chip,VLSI processor design,packing density,2 micron,floorplanning,vlsi processor,ADPCM CODEC,high-speed operation,macrocell approach,standard cell layout,circuit layout CAD,design productivity,digital signal processing chips,application program,CMOS technology,functional blocks,cellular arrays,16 bits,effective layout design method,vlsi processor design,flexible symbolic layout method,layout design method,productivity,automatic layout program,symbolic layout,digital signal processor | Journal | 7 |
Issue | ISSN | Citations |
12 | 0278-0070 | 1 |
PageRank | References | Authors |
0.46 | 3 | 8 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| T. Tokuda | 1 | 1 | 0.46 |
| J. Korematsu | 2 | 3 | 0.93 |
| Y. Shimazu | 3 | 1 | 0.46 |
| N. Sakashita | 4 | 1 | 0.46 |
| T. Kengaku | 5 | 2 | 0.94 |
| T. Fugiyama | 6 | 1 | 0.46 |
| T. Ohno | 7 | 1 | 0.46 |
| O. Tomisawa | 8 | 3 | 0.93 |