Name
Abstract | ||
|---|---|---|
A fundamental challenge to successful deployment of DRAMs is the availability of a flexible and scalable DRAM interface. This is exacerbated by the application specific nature of the logic-side DRAM interface. This paper presents a study that attempts to overcome this challenge for networking application domain. We quantify the various challenges and present techniques that were implemented to build a flexible and scalable interface to an existing multi-port memory controller for DDR DRAM using a FPGA. We demonstrate the deployment of this new interface in two example applications. We present two novel techniques that enable us to reduce the latency of DRAM related memory accesses and improve throughput. We believe our techniques enable harnessing maximum throughput from existing memory controllers with least possible latency. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1145/1117201.1117258 | FPGA |
Keywords | Field | DocType |
existing multi-port memory controller,new interface,networking application,scalable dram interface,example application,logic-side dram interface,application specific nature,dram related memory access,scalable interface,ddr dram,memory controller,ip,discrete fourier transform | Dram,Software deployment,Computer science,Latency (engineering),Parallel computing,Field-programmable gate array,Real-time computing,Application domain,Throughput,Memory controller,Scalability,Embedded system | Conference |
ISBN | Citations | PageRank |
1-59593-292-5 | 0 | 0.34 |
References | Authors | |
8 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jike Chong | 1 | 136 | 11.62 |
| Chidamber Kulkarni | 2 | 123 | 15.18 |
| Gordon Brebner | 3 | 155 | 15.41 |